The present invention relates to automatic data processing, and more specifically concerns apparatus and methods for transferring multi-byte data efficiently by cycle-steal (sometimes called direct memory access or DMA) operations between a processing engine and multiple input/output devices in a data-processing system.
Conventional data processors have input/output (I/O) devices connected to a system channel either directly via a device adapter or in clusters each having a cluster controller. Since the channel has a much higher data rate than any I/O device, each adapter and/or cluster controller commonly includes its own data buffer capable of holding an entire block of data for transfer to or from the channel in a single multi-byte burst. This leads to the use of a large number of such buffers in the processor. Each must be designed to interface to its own device on a byte-by-byte protocol as well as to the common channel on a block-multiplexed (burst-multiplexed) protocol. Each buffer and its protocol translator costs money, consumes power, and occupies board space, even though its usage is much less than full-time. This is a wasteful situation.